1. Field of the Invention
The present invention relates to a structure of a thin film transistor in which its withstand voltage characteristics and leak current characteristics are improved. The present invention also relates to a method of manufacturing the thin film transistor.
2. Description of the Related Art
In recent years, there has been known a technique in which a thin film semiconductor film is formed on a glass substrate or a quartz substrate and a transistor is manufactured by using the film as an active layer. This transistor is generically referred to as a thin film transistor. The thin film transistor will be hereinafter referred to as a TFT.
In general, as a semiconductor thin film for forming an active layer of a TFT, an amorphous silicon film or a crystalline silicon film (polycrystalline film or microcrystalline film) is used. This is because a single crystal silicon film can not be formed on a glass substrate or a quartz substrate by an existing technique.
Although low withstand voltage and large OFF-state current value do not become a subject of discussion in a TFT using an amorphous silicon film since its total characteristics are also low, they become a problem in a TFT using a crystalline silicon film.
This problem is caused because the density of defects existing in the silicon film is extremely high as compared with single crystal silicon.
As means for solving the problem, there are known structures disclosed in Japanese Patent Publication No. Hei. 3-38755 and Japanese Patent Unexamined Publication Nos. Hei. 4-360580 and Hei. 5-166837. 
The structures disclosed in the above publications are referred to as an LDD technique or an offset technique. In these techniques, a high resistance region, which does not function as a channel or a drain, is disposed between a channel region and a drain region, so that a high electric filed applied between the channel region and the drain region is relaxed.
At an OFF operation, the movement of carriers via defects present in the vicinity of the boundary between the channel region and the drain region is suppressed.
The type of high resistance region is roughly divided into a structure of a non-doped region (generically referred to as an offset structure) and a structure of a lightly doped region (generically referred to as an LDD structure).
Japanese Patent Unexamined Publication Nos. Hei. 4-360580 and Hei. 5-166837 disclose a technique as a method of forming a high resistance region in which an anodic oxidation film is formed on the surface of a gate electrode and the high resistance region is formed in a self-aligning manner by the thickness of the anodic oxidation film.
This method has a feature that the high resistance region can be formed with high controllability.
An object of the present invention is to provide a TFT with a novel structure in which its withstand voltage is high and OFF-state current is small.
According to a first aspect of the present invention, a thin film transistor comprises an active layer composed of some regions, a gate insulating film of a silicon oxide film formed on the active layer, and a gate electrode formed on the gate insulting film, and is characterized in that the active layer has been subjected to oxidation using the gate electrode as a mask, and the shape of a certain portion of the gate insulating film is different from that of the other portion thereof.
The certain portion is formed by thermal oxidation using the gate electrode as a mask. In this portion, the thermal oxidation in the active layer progresses to a region under the gate electrode.
In this state, the end of the upper portion of a channel region formed in the active layer is selectively oxidized. By making such a structure, it is possible to realize the state in which the thickness of the gate insulating film at the end of the upper portion of the channel gradually becomes thicker in the direction from the channel to a source or from the channel to a drain.
According to another aspect of the present invention, a method of manufacturing a thin film transistor comprises the steps of: forming a silicon oxide film on an active layer; forming a gate electrode on the silicon oxide film; and carrying out thermal oxidation using the gate electrode as a mask to increase the thickness of the silicon oxide film except a portion; and is characterized in that the end of the region subjected to the thermal oxidation extends to the portion under the gate electrode.
In this structure, the end of the upper portion of the channel region is selectively oxidized. That is, the thermal oxidation progresses to the end of the upper portion of the channel region.
By adopting this structure, the thickness of the gate insulating film at the end of the upper portion of the channel region is gradually changed. That is, it is possible to obtain such a structure that the thickness of the gate insulating film gradually becomes thicker in the direction from the end of the upper portion of the channel region to the source/drain regions.
The silicon oxide film prior to the thermal oxidation may be a silicon oxide film having an incomplete constitution. This film may contain an element other than oxygen and silicon if the film has such a film quality that thermal oxidation progresses.
In the manufacturing steps of the present invention, after the gate insulating film of the silicon oxide film is formed, the gate electrode is formed, and then the thermal oxidation is carried out.
By this, the thermal oxidation progresses in the portion except the region where the gate electrode is disposed, and the thickness of the portion becomes thick. The thermal oxidation also progresses to a portion under the gate electrode.
In this way, a state in which the thickness of the gate insulating film is gradually changed, is obtained in this portion. That is, there is obtained such a state that the thickness of the gate insulating film becomes thicker in the direction from the end of the upper portion of the channel region to the source/drain regions.
By this, it is possible to realize the structure in which the electric field applied to the active layer from the gate electrode is gradually weakened correspondingly to the change of the thickness of the gate insulating film in the direction from the end of the upper portion of the channel region to the source/drain regions.
The inversion layer formed on the end of the upper portion of the channel region can be made weak as compared with that on the center of the channel, and there is obtained an effect similar to the case where a lightly doped region or an offset region is formed.
That is, it is possible to realize the structure in which the electric field applied between the channel region and the drain region can be made weak.